The metal contacts of semiconductor devices to the ridge or mesa structures of the devices are typically formed by creating a via hole through the passivation layer. The position of this via hole is defined by aligning a mask during a photolithography process. Because of the tolerance limit of the lithography process, the width of this via hole normally is significantly smaller than the width of the area of the semiconductor where the metal contact is to be created. This results in small metal contact areas and uneven distribution of the current in the mesa area, which in turn will result in a high device driving voltage. This problem is particularly critical for GaN based devices since the p-type nitride semiconductor material has a relatively low carrier mobility and a low active carrier concentration. Accordingly, p-type nitride semiconductor material normally shows a relatively high resistivity. Hence, it is beneficial for the ohmic contact to p-type nitride material to cover as much surface area as possible.
It is also a challenge to make metal contacts to small feature sized semiconductor devices, e.g. with a mesa or ridge dimension less than 1 μm. Normal photolithography reaches its limitation at this range.
Due to the above mentioned disadvantages of photolithography processes for making metal contacts to semiconductor devices, a number self-aligned technologies have been proposed. In one such self-aligned technology described in U.S. Pat. No. 6,210,997, sidewall oxidation is utilised to form the passivation layer of the semiconductor device. However, the sidewall oxidation method has a number of disadvantages, including that where thermal oxidation is used, high temperatures are required which may adversely effect the semiconductor device and is also believed to be effective only for high aluminium content materials. On the other hand, if anodic oxidation is used, a current is needed to assist the oxidation process, which is not typically acceptable in semiconductor fabrication processes.
In another self-aligned technique described in US patent publication no. 2006/00451555, a metal contact layer is used as mesa or ridge etching mask. Such a method has the disadvantage of etching of metals not being compatible to a number of semiconductor processes, like for InP and GaAs based semiconductor devices.
In another self-aligned technique described in US patent publication no. 2004/0218648, dielectric etch back is utilised to make the self-aligned metal contact, utilising a multi-step dielectric plasma etching process. This method has the disadvantage associated with performing a plasma etching process, which can cause damage to the semiconductor surface during the plasma etching of the dielectric material on top of the contact area.
In another method described in U.S. Pat. No. 6,846,740, polymer reflow is utilised to form the passivation layer of the semiconductor device. This method has the disadvantage that the polymer can limit high temperature semiconductor processes after passivation. For example, metal alloying to form an ohmic contact in GaN based semiconductor devices typically requires a temperature of 500° C.-600° C., where a polymer based passivation layer is unsuitable.
On the other hand, light extraction in semiconductor light emitting devices is one of the important factors in enhancing the device efficiency. Although pillar-structured surface textures or pillar-structured LED arrays were found to enhance device efficiency, it is a challenge to make ohmic contact to a pillared device structure. Sidewall passivation in a semiconductor device is required to prevent current leakage and short circuits and also to protect the device from environmental conditions. However, existing techniques typically spread a metal layer over the entire surface without a passivation layer on the sidewall of the etched pattern.
A need therefore exists to provide a self-aligned metal contact formation technique which seeks to address at least one of the above mentioned problems.